Synthesis of Low Power CMOS Circuits Using Pass Logic Topology

in recent years, with the increasing demand for high-performance portable electronic devices such as laptop cornputers and cellular phones, power dissipation has become a very important performance parameter in VLSI design. One approach to power reduction hvolves the use of circuit topologies different fiom the standard CMOS topology. A probiem with this approach is that there is a lack of design automation tools available that can take full advantage of these aitemate topologies. This thesis describes the design of a logic synthesis tool designed specifically to work with a ce11 library based on pass logic multiplexers. The goal is to achieve optimized circuits realized with lower power consumption compared to those generated with a standard CMOS ce11 library. The ce11 library is cornposed of a combination of pass logic multiplexer cells and standard CMOS cells. Al1 cells are based on the CMOSISS 0 . 5 ~ process available from the Canadian Microelectronics Corporation.